The material generally used to form the gate of an MOS transistor, in particular in the case of short-channel transistors (channel length less than 0.18 μm) is polycrystalline silicon (poly-silicon or poly-Si). Conventionally, the gates of these transistors are obtained by high-density plasma etching of a poly-Si layer deposited on a thin layer of dielectric (gate dielectric), typically made of silicon oxide (SiO2), formed on the surface of a single-crystal silicon substrate.
At the present time it is sought to replace the SiO2 layer with a layer of a dielectric having a high dielectric permittivity (high-k material) for low-energy-consumption applications requiring a low leakage current. The introduction of high-k materials for the purpose of replacing SiO2 must firstly be accomplished with a standard poly-Si gate.
In recent years, attempts have been made to develop high-k material as much as the poly-Si gate. It seems that the metal-oxide-type materials investigated hitherto are incompatible with a standard poly-Si gate deposition process. On this subject, the reader may refer to the article “Compatibility of Polycrystalline Silicon Gate Deposition with HfO2 and HfO2/Al2O3 Gate Dielectrics” by D.C. Gilmer et al., MOTOROLA (APL, Vol. 81, No 7, pp 1288–1290). This is because a large number of short-circuit-type defects are generated, of the order of 104 defects per cm2.
From studies and observations made by the inventors, which are the basis of the present invention, it is considered that the appearance of these defects is probably due to direct interaction between, on the one hand, the gases used during deposition of the poly-Si gate, namely silane (SiH4) and hydrogen (H2), and, on the other hand, the surface of the high-k material, owing to the high temperature, of around, but not limited to, 550° C., at which this deposition is carried out. When the high-k material is a layer of hafnium oxide (HfO2), the interaction in this case is an Hf/Si-type interaction that occurs at temperatures of around, but not limited to, 550° C. or higher.
To alleviate this problem, two approaches are in principle conceivable: the first would be to modify the high-k material and the second would be to modify the gate.
Regarding the first approach, it is known that many studies have been carried out in order to modify the high-k material, but this generally results either in a reduction in the dielectric permittivity (k) or in an increase in the number of fixed charges in the material, having the effect of degrading the characteristics of the transistors. On this subject, the reader may refer to the article “Effect of Nitrogen in HfSiON Gate Dielectrics on the Electrical and Thermal Characteristics” M. Koyoma et al., Toshiba Corporation (IEDM 2002), which is hereby incorporated by reference in its entitety.
As regards the second approach, it is also known that the use of a metallic gate, especially a gate made of titanium nitride (TiN), does admittedly avoid the problem of generating defects, but it poses many problems of integration and of compatibility with an FEOL (Front-End Of the Line) process. In particular, it is preferable to maintain a poly-Si gate that offers the possibility of n-doping or p-doping by ion implantation.
Moreover EP-A1-0 887 843 teaches a transistor having a Si/SiGe composite gate, that comprises a SiO2 layer on a Si semiconductor substrate, a Si tie layer with a thickness of less than or equal to 1 nm on the SiO2 layer, and a polycrystalline Si1−xGex layer, where 0<x≦y, with a thickness of around, but not limited to, 2 to 20 nm, on this tie layer, the Si1−xGex being surmounted by a Si layer. The tie layer is deposited at a temperature of between 500 and 580° C., typically 550° C. This is why the aforementioned interactions of the Hf—Si type would occur at the interface with the layer of high-k material if such a layer were to replace the SiO2 layer.
According what is needed is a method and system to over come the problems encountered in the prior art and to provide a transistor gate that is less aggressive with respect to the high-k material in the first steps of depositing the gate, but that is also compatible with the conventional fabrication processes, especially including the adjustment of the gate work function by ion implantation.